Seven strategies for tolerating highly defective fabrication
DeHon, A.
Naeimi, H.
California Inst. of Technol., Pasadena, CA, USA;
This paper appears in: Design & Test of Computers, IEEE
Publication Date: July-Aug. 2005
Volume: 22,
Issue: 4
On page(s): 306- 315
ISSN: 0740-7475
INSPEC Accession Number: 8524487
Digital Object Identifier: 10.1109/MDT.2005.94
Current Version Published: 2005-08-08
Abstract
This article we present an architecture that supports fine-grained sparing and resource matching. The base logic structure is a set of interconnected PLAs. The PLAs and their interconnections consist of large arrays of interchangeable nanowires, which serve as programmable product and sum terms and as programmable interconnect links. Each nanowire can have several defective programmable junctions. We can test nanowires for functionality and use only the subset that provides appropriate conductivity and electrical characteristics. We then perform a matching between nanowire junction programmability and application logic needs to use almost all the nanowires even though most of them have defective junctions. We employ seven high-level strategies to achieve this level of defect tolerance.
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