The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA Implementation
Sridharan, K.
Priya, T.K.
This paper appears in: Industrial Electronics, IEEE Transactions on
Publication Date: Aug. 2005
Volume: 52,
Issue: 4
On page(s): 1185- 1187
ISSN: 0278-0046
Digital Object Identifier: 10.1109/TIE.2005.851591
Current Version Published: 2005-08-01
Abstract
A valuable geometric structure in mobile robot path planning is the complete visibility graph. This letter proposes new parallel algorithms that can be mapped to reconfigurable hardware for construction of the complete visibility graph in an environment with: 1) multiple convex polygonal objects and 2) multiple nonconvex polygonal objects. Results of implementation in a Xilinx Virtex field-programmable gate array demonstrate that the proposed approach is area–time efficient: the design for an environment with roughly 60 vertices fits on one XCV3200E device and operates at close to 60 MHz.
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