An energy efficient instruction set synthesis framework for low power embedded system designs
Cheng, A.C.
Tyson, G.S.
Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA;
This paper appears in: Computers, IEEE Transactions on
Publication Date: Jun 2005
Volume: 54,
Issue: 6
On page(s): 698- 713
ISSN: 0018-9340
INSPEC Accession Number: 8441483
Digital Object Identifier: 10.1109/TC.2005.89
Current Version Published: 2005-07-18
Abstract
Energy efficiency, performance, area, and cost are critical concerns in designing microprocessors for embedded systems such as portable handheld computing and personal telecommunication devices. This work introduces the concept of framework-based instruction set synthesis (FITS), which is a new instruction synthesis paradigm that falls between a general-purpose embedded processor and a synthesized application specific processor (ASP). FITS processors reduce code size and energy consumption by tailoring the instruction set to the requirement of a target application. This is achieved by replacing the fixed instruction and register decoding of a general purpose embedded processor with programmable decoders that can achieve ASP performance, low energy consumption, and smaller code size with the fabrication advantages of a mass produced single chip solution. Experimental results show that our synthesized instruction sets result in significant power reduction in the level one instruction cache compared to ARM instructions. The instruction cache is one of the most predominant sources of power dissipation on the processor. For instance, in Intel's StrongARM processor, 27 percent of total chip power loss goes into the instruction cache. For 21 MiBench benchmarks, our simulation results, indicate, on average, a 49.4 percent saving for switching power, a 43.9 percent saving for internal power, a 14.9 percent saving for leakage power, a 46.6 percent saving for total instruction cache power with up to 60.3 percent saving for peak power.
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