Using the multilevel imbricated cells topologies in the design of low-power power-factor-corrector converters
Forest, F.
Meynard, T.A.
Faucher, S.
Richardeau, F.
Huselstein, J.-J.
Joubert, C.
Lab. d'Electrotechnique de Montpellier, Univ. de Montpellier, France;
This paper appears in: Industrial Electronics, IEEE Transactions on
Publication Date: Feb. 2005
Volume: 52,
Issue: 1
On page(s): 151- 161
ISSN: 0278-0046
INSPEC Accession Number: 8275538
Digital Object Identifier: 10.1109/TIE.2004.841097
Current Version Published: 2005-02-07
Abstract
Power-factor-corrector (PFC) converters are now commonly used in low-power supply systems connected to AC networks. In addition to their basic PFC properties, they constitute the best technical solution to directly obtain the compatibility with a large range of AC voltages provided by different distribution networks around the world (typically, from 85 to 265 V rms). It is the main application of these converters. This function is achieved with an additional cost and volume, and this extra price to pay needs to be minimized. In this context, we first recall the main approaches of the design of conventional PFCs based on the boost converter topology. We emphasize the different critical points of the sizing that mainly concern the input choke and the silicon devices, in regard with the choice of the switching frequency. Few ways of improvement are then presented for these conventional PFCs. In a second part, always in the context of a large input voltage range, we consider the possibility to introduce the multi-level concept to reduce the input choke and filters. A solution using a multi-level flying capacitor two-cell converter is presented. It is shown that it can lead to a significant increase of the performances, with several options of sizing which can be suited to different requirements of the applications.
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