Abstract
Algorithms, software tools and the relevant methodology for production yield optimization with respect to fundamental technological parameters of the IC manufacturing process (such as diffusion times and temperatures) and element layout mask dimensions are discussed. The tools developed include: STOCH-PAC--a package of new yield optimization and yield gradient estimation algorithms based on Stochastic Approximation approach and the Method of Random Perturbations; YIELD-PAC - a package of yield evaluation subroutines providing an interface to SPICE-PAC circuit simulation package; FABPAC - an interface to the FABRICS statistical process simulator; and IRIS (Interactive Restructurable Interface System)--a flexible user interface for efficient data manipulation, creation of different design tasks and macrotasks, restructuring the set of active subroutines, etc. These tools have been integrated into the TOY (Technological Optimization of Yield) program. Examples of yield optimization with respect to process parameters and layout dimensions using TOY are given.
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