Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation
Girczyc, E.F.
Buhr, R.J.A.
Knight, J.P.
Abstract
The requirements of an algorithmic level hardware description language can be met by a software language with only limited feature enhancement. This paper discusses the feasibility of using a subset of Ada as a hardware description language. Methods are presented for realizing the extra features required for hardware description within the syntax of Ada. This allows the compiled Ada program to act as a functional simulator. Our particular context for hardware description is as a source language for a hardware compiler. Rules are presented for translating a circuit described in the Ada subset onto a control/data-flow graph (CDFG), our intermediate level form.
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