An area model for on-chip memories and its application
Mulder, J.M.
Quach, N.T.
Flynn, M.J.
Dept. of Electr. Eng., Delft Univ. of Technol. ;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Feb 1991
Volume: 26,
Issue: 2
On page(s): 98-106
ISSN: 0018-9200
References Cited: 27
CODEN: IJSCBC
INSPEC Accession Number: 3891122
Digital Object Identifier: 10.1109/4.68123
Current Version Published: 2002-08-06
Abstract
An area model suitable for comparing data buffers of different
organizations (e.g. caches versus register files) and arbitrary sizes is
described. The area model considers the supplied bandwidth of a memory
cell and includes such buffer overhead as control logic, driver logic
and tag storage. The model gave less than 10% error when verified
against real caches and register files. It is shown that, comparing
caches and register files in terms of area for the same storage
capacity, caches generally occupy more area per bit than register files
for small caches because the overhead dominates the cache area at these
sizes. For larger caches, the smaller storage cells in the cache provide
a smaller total cache area per bit than the register set. Studying cache
performance (traffic ratio) as a function of area, it is shown that, for
small caches (less than the area occupied by 256 registers
bits-r.b.e.-or 32 b), direct-mapped caches perform significantly better
than four-way set-associative caches and, for caches of medium areas
(between 256 r.b.e. and 4096 r.b.e.), both direct-mapped and
set-associative caches perform better than fully associative
caches
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