A network on chip architecture and design methodology
Kumar, S.
Jantsch, A.
Soininen, J.-P.
Forsell, M.
Millberg, M.
Oberg, J.
Tiensyrja, K.
Hemani, A.
Lab. of Electron. & Comput. Syst., R. Inst. of Technol., Stockholm;
This paper appears in: VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on
Publication Date: 2002
On page(s): 105-112
Meeting Date: 04/25/2002 - 04/26/2002
Location: Pittsburgh, PA, USA
ISBN: 0-7695-1486-3
References Cited: 20
INSPEC Accession Number: 7328291
Digital Object Identifier: 10.1109/ISVLSI.2002.1016885
Current Version Published: 2002-08-07
Abstract
We propose a packet switched platform for single chip systems
which scales well to an arbitrary number of processor like resources.
The platform, which we call Network-on-Chip (NOC), includes both the
architecture and the design methodology. The NOC architecture is a
m×n mesh of switches and resources are placed on the slots formed
by the switches. We assume a direct layout of the 2-D mesh of switches
and resources providing physical- and architectural-level design
integration. Each switch is connected to one resource and four
neighboring switches, and each resource is connected to one switch. A
resource can be a processor core, memory, an FPGA, a custom hardware
block or any other intellectual property (IP) block, which fits into the
available slot and complies with the interface of the NOC. The NOC
architecture essentially is the onchip communication infrastructure
comprising the physical layer, the data link layer and the network layer
of the OSI protocol stack. We define the concept of a region, which
occupies an area of any number of resources and switches. This concept
allows the NOC to accommodate large resources such as large memory
banks, FPGA areas, or special purpose computation resources such as high
performance multi-processors. The NOC design methodology consists of two
phases. In the first phase a concrete architecture is derived from the
general NOC template. The concrete architecture defines the number of
switches and shape of the network, the kind and shape of regions and the
number and kind of resources. The second phase maps the application onto
the concrete architecture to form a concrete product
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
