Reliability of low temperature poly-silicon TFTs under inverter operation

We have studied the reliability of low-temperature polycrystalline-silicon thin-film-transistors (TFTs) under dynamic bias stress using a CMOS inverter circuit. A remarkable decrease in the mobility and the ON-current was observed in n-channel TFTs under dynamic stress. The degradation depends strongly on the falling edge of the voltage pulse and the number of pulses. Observation by emission microscopy revealed that hot electrons were generated around the edge of the drain region in the n-channel TFT. We also confirmed that TFTs with lightly doped drain were less degraded. Based on these experimental results, a new degradation model was proposed. The model suggests that upon the gate voltage drop, electrons move rapidly to the drain, thus, becoming hot and creating electron traps in the grain boundaries around the drain. Consequently, the ON-current is decreased.