The future of wires
Ho, R.
Mai, K.W.
Horowitz, M.A.
Dept. of Comput. Sci., Stanford Univ., CA;
This paper appears in: Proceedings of the IEEE
Publication Date: Apr 2001
Volume: 89,
Issue: 4
On page(s): 490-504
ISSN: 0018-9219
References Cited: 56
CODEN: IEEPAD
INSPEC Accession Number: 6929676
Digital Object Identifier: 10.1109/5.920580
Current Version Published: 2002-08-07
Abstract
Concern about the performance of wires wires in scaled
technologies has led to research exploring other communication methods.
This paper examines wire and gate delays as technologies migrate from
0.18-μm to 0.035-μm feature sizes to better understand the
magnitude of the the wiring problem. Wires that shorten in length as
technologies scale have delays that either track gate delays or grow
slowly relative to gate delays. This result is good news since these
“local” wires dominate chip wiring. Despite this scaling of
local wire performance, computer-aided design (CAD) tools must still
become move sophisticated in dealing with these wires. Under scaling,
the total number of wires grows exponentially, so CAD tools will need to
handle an ever-growing percentage of all the wires in order to keep
designer workloads constant. Global wires present a more serious problem
to designers. These are wires that do not scale in length since they
communicate signals across the chip. The delay of these wives will
remain constant if repeaters are used meaning that relative to gate
delays, their delays scale upwards. These increased delays for global
communication will drive architectures toward modular designs with
explicit global latency mechanisms
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