Abstract
Global interconnect is commonly regarded as a key potential
bottleneck to the advancing performance of high-speed integrated
circuits. Our previous work has suggested that local interconnect
effects can be managed through a deep submicron design hierarchy that
uses 50000 to 100000 gate modules as primitive building blocks. The
primary goal of this paper is to examine global interconnect effects,
within such a design hierarchy, to determine if there are any
significant roadblocks which will prevent National Technology Roadmap
for Semiconductors (NTRS) performance expectations from being met.
Specifically, the issues of global resistance-capacitance delay, signal
time-of-flight, inductance, clock and power distribution, and noise are
studied. Results indicate that, while global clock frequencies will
necessarily he lower than local clock speeds, NTRS expectations should
be attainable to the 50 nm technology generation. Achieving these high
clock speeds (10 GHz local clock) will be aided by the use of a newly
proposed routing hierarchy which limits interconnect effects at each
level of a design (local, isochronous, and global)
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