Dynamic and transparent binary translation
Gschwind, M.
Altman, E.R.
Sathaye, S.
Ledak, P.
Appenzeller, D.
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY;
This paper appears in: Computer
Publication Date: Mar 2000
Volume: 33,
Issue: 3
On page(s): 54-59
ISSN: 0018-9162
References Cited: 6
CODEN: CPTRB4
INSPEC Accession Number: 6531408
Digital Object Identifier: 10.1109/2.825696
Current Version Published: 2002-08-06
Abstract
High-frequency design and instruction-level parallelism (ILP) are
important for high-performance microprocessor implementations. The
Binary-translation Optimized Architecture (BOA), an implementation of
the IBM PowerPC family, combines binary translation with dynamic
optimization. The authors use these techniques to simplify the hardware
by bridging a semantic gap between the PowerPC's reduced instruction set
and even simpler hardware primitives. Processors like the Pentium Pro
and Power4 have tried to achieve high frequency and ILP by implementing
a cracking scheme in hardware: an instruction decoder in the pipeline
generates multiple micro-operations that can then be scheduled out of
order. BOA relies on an alternative software approach to decompose
complex operations and to generate schedules, and thus offers
significant advantages over purely static compilation approaches. This
article explains BOA's translation strategy, detailing system issues and
architecture implementation
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