Abstract
Simultaneous Multi-Threading (SMT) is a hardware technique that
increases processor throughput by issuing instructions simultaneously
from multiple threads. However, while SMT can be added to an existing
microarchitecture with relatively low overhead, this additional chip
area could be used for other resources such as more functional units,
larger caches or better branch predictors. How large is the SMT
overhead, and at what point does SMT no longer pay off compared to
adding other architecture features? This paper evaluates the silicon
overhead of SMT by performing a transistor/interconnect level analysis
of the layout. We discuss micro-architecture issues that impact SMT
implementations, and show how the Instruction Set Architecture (ISA) and
microarchitecture can have a large effect on the SMT overhead and
performance. Results show that SMT yields large performance gains with
small to moderate area overhead
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