Neuro-fuzzy architecture for CMOS implementation
Wilamowski, B.M.
Jaeger, R.C.
Kaynak, M.O.
Dept. of Electr. Eng., Wyoming Univ., Laramie, WY ;
This paper appears in: Industrial Electronics, IEEE Transactions on
Publication Date: Dec 1999
Volume: 46,
Issue: 6
On page(s): 1132-1136
ISSN: 0278-0046
References Cited: 14
CODEN: ITIED6
INSPEC Accession Number: 6443311
Digital Object Identifier: 10.1109/41.808001
Current Version Published: 2002-08-06
Abstract
In this paper, a nonconventional structure for a
“fuzzy” controller is proposed. It does not require signal
division, and it produces control surfaces similar to classical fuzzy
controllers. The structure combines fuzzification, MIN operators,
normalization, and weighted sum blocks. The fuzzy architecture is
implemented as a VLSI chip using 2-μm n-well technology. A new
fuzzification circuit, which requires only one differential pair per
membership function is proposed. Eight equally spaced membership
functions are used in the VLSI implementation. Simple voltage MIN
circuits are used for rule selection. A modified Takagi-Sugeno approach
with normalization and weighted sum is used in the defuzzification
circuit. Weights in the defuzzifier are digitally programmable with
6-bits resolution
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
