Baring it all to software: Raw machines
Waingold, E.
Taylor, M.
Srikrishna, D.
Sarkar, V.
Lee, W.
Lee, V.
Kim, J.
Frank, M.
Finch, P.
Barua, R.
Babb, J.
Amarasinghe, S.
Agarwal, A.
MIT, Cambridge, MA;
This paper appears in: Computer
Publication Date: Sep 1997
Volume: 30,
Issue: 9
On page(s): 86-93
ISSN: 0018-9162
References Cited: 7
CODEN: CPTRB4
INSPEC Accession Number: 5699446
Digital Object Identifier: 10.1109/2.612254
Current Version Published: 2002-08-06
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The most radical of the architectures that appear in this issue
are Raw processors-highly parallel architectures with hundreds of very
simple processors coupled to a small portion of the on-chip memory. Each
processor, or tile, also contains a small bank of configurable logic,
allowing synthesis of complex operations directly in configurable
hardware. Unlike the others, this architecture does not use a
traditional instruction set architecture. Instead, programs are compiled
directly onto the Raw hardware, with all units told explicitly what to
do by the compiler. The compiler even schedules most of the intertile
communication. The real limitation to this architecture is the efficacy
of the compiler. The authors demonstrate impressive speedups for simple
algorithms that lend themselves well to this architectural model, but
whether this architecture will be effective for future workloads is an
open question
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