A submicron DC MOSFET model for simulation of analog circuits
Chatterjee, A.
Machala, C.F., III
Ping Yang
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX;
Abstract
This paper presents an efficient dc MOSFET model for accurate
simulation of analog circuits. A new approach to model channel length
modulation is presented. An empirical expression for channel length
modulation is derived from measurements. This is used to model the
observed behavior of gD with gate, drain, and substrate bias.
Some of the models commonly used for circuit simulation do not predict
the effects of gate and substrate bias adequately. A new smoothing
function is used to unify the linear and saturation regions in a single
expression. Continuity of transconductance is maintained between the
weak and strong inversion regions. Model efficiency is maintained by
avoiding the use of transcendental functions in the smoothing
techniques. We demonstrate <2.5% rms error in predicting
ID, gD, and gm for a discrete device
size and <4% rms error for models scalable over a wide range of width
and length. Furthermore, we have experimentally characterized a CMOS
inverter as well as an op-amp to show that our model improves prediction
of circuit parameters. Errors in predicting the peak gains are reduced
by at least half compared to earlier models
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