FlowMap: an optimal technology mapping algorithm for delayoptimization in lookup-table based FPGA designs
Cong, J.
Yuzheng Ding
Dept. of Comput. Sci., California Univ., Los Angeles, CA;
Abstract
The field programmable gate-array (FPGA) has become an important
technology in VLSI ASIC designs. In the past few years, a number of
heuristic algorithms have been proposed for technology mapping in
lookup-table (LUT) based FPGA designs, but none of them guarantees
optimal solutions for general Boolean networks and little is known about
how far their solutions are away from the optimal ones. This paper
presents a theoretical breakthrough which shows that the LUT-based FPGA
technology mapping problem for depth minimization can be solved
optimally in polynomial time. A key step in our algorithm is to compute
a minimum height K-feasible cut in a network, which is solved optimally
in polynomial time based on network flow computation. Our algorithm also
effectively minimizes the number of LUT's by maximizing the volume of
each cut and by several post-processing operations. Based on these
results, we have implemented an LUT-based FPGA mapping package called
FlowMap. We have tested FlowMap on a large set of benchmark examples and
compared it with other LUT-based FPGA mapping algorithms for delay
optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap
reduces the LUT network depth by up to 7% and reduces the number of
LUT's by up to 50% compared to the three previous methods
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
