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System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
Jingcao Hu Umit Y. Ogras Radu Marculescu
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;

This paper appears in: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publication Date: Dec. 2006
Volume: 25, Issue: 12
On page(s): 2919-2933
Location: Sonoma, CA, USA,
ISSN: 0278-0070
INSPEC Accession Number: 9311133
Digital Object Identifier: 10.1109/TCAD.2006.882474
Current Version Published: 2006-11-20

Abstract
In this paper, a novel system-level buffer planning algorithm that can be used to customize the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic characteristics of the target application and the total budget of the available buffering space, the proposed algorithm automatically assigns the buffer depth for each input channel, in different routers across the chip, such that the overall performance is maximized. This is in deep contrast with the uniform assignment of buffering resources (currently used in NoC design), which can significantly degrade the overall system performance. Indeed, the experimental results show that while the proposed algorithm is very fast, significant performance improvements can be achieved compared to the uniform buffer allocation. For instance, for a complex audio/video application, about 80% savings in buffering resources, can be achieved by smart buffer allocation using the proposed algorithm

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