Making typical silicon matter with Razor
Austin, T.
Blaauw, D.
Mudge, T.
Flautner, K.
Michigan Univ., MI, USA;
This paper appears in: Computer
Publication Date: Mar 2004
Volume: 37,
Issue: 3
On page(s): 57- 65
ISSN: 0018-9162
INSPEC Accession Number: 7915846
Digital Object Identifier: 10.1109/MC.2004.1274005
Current Version Published: 2004-08-02
Abstract
Voltage scaling has emerged as a powerful technology for addressing the power challenges that current on-chip densities pose. Razor is a voltage-scaling technology based on dynamic, in-situ detection and correction of circuit-timing errors. Razor permits design optimizations that tune the energy in a microprocessor pipeline to typical circuit-operational levels. This eliminates the voltage margins that traditional worst-case design methodologies require and lets digital systems run correctly and robustly at the edge of minimum power consumption. Occasional heavyweight computations may fail and require additional time and energy for recovery, but the optimized pipeline requires significantly less energy overall than traditional designs.
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