An automatic circuit diagram reader with loop-structure-basedsymbol recognition
Okazaki, A.
Kondo, T.
Mori, K.
Tsunekawa, S.
Kawamoto, E.
Toshiba Res. & Dev. Center, Kawasaki;
This paper appears in: Pattern Analysis and Machine Intelligence, IEEE Transactions on
Publication Date: May 1988
Volume: 10,
Issue: 3
On page(s): 331-341
ISSN: 0162-8828
References Cited: 18
CODEN: ITPIDJ
INSPEC Accession Number: 3191493
Digital Object Identifier: 10.1109/34.3898
Current Version Published: 2002-08-06
Abstract
A high-performance logic circuit diagram reader was developed for
VLSI-CAD data input. Almost all logic circuit symbols include one or
more loop structures. A description is given of an efficient method for
recognition of these loop-structured symbols. The proposed method
consists of two processes: symbol segmentation and symbol
identification. Symbol identification is achieved by a powerful hybrid
method which uses heuristics to mediate between template matching and
feature extraction. The entire symbol recognition process is carried out
under a decision-tree control strategy. The entire recognition system
for circuit diagrams is briefly explained, including character string
recognition and connecting line analysis
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