High throughput low-density parity-check decoder architectures
Yeo, E.
Pakzad, P.
Nikolic, B.
Anantharam, V.
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;
This paper appears in: Global Telecommunications Conference, 2001. GLOBECOM '01. IEEE
Publication Date: 2001
Volume: 5,
On page(s): 3019-3024 vol.5
Meeting Date: 11/25/2001 - 11/29/2001
Location: San Antonio, TX, USA
ISBN: 0-7803-7206-9
References Cited: 9
INSPEC Accession Number: 7313766
Digital Object Identifier: 10.1109/GLOCOM.2001.965981
Current Version Published: 2002-08-06
Abstract
Two decoding schedules and the corresponding serialized
architectures for low-density parity-check (LDPC) decoders are
presented. They are applied to codes with parity-check matrices
generated either randomly or using geometric properties of elements in
Galois fields. Both decoding schedules have low computational
requirements. The original concurrent decoding schedule has a large
storage requirement that is dependent on the total number of edges in
the underlying bipartite graph, while a new, staggered decoding schedule
which uses an approximation of the belief propagation, has a reduced
memory requirement that is dependent only on the number of bits in the
block. The performance of these decoding schedules is evaluated through
simulations on a magnetic recording channel
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