Home  |   Login  |   Logout  |   Access Information  |   Alerts  |   Purchase History  |   Cart  |   Sitemap  |   Help   
 
Abstract
BROWSE SEARCH IEEE XPLORE GUIDE SUPPORT
arrow_leftView TOC
Email/Printer Friendly Format  
 

Minimum area layout of series-parallel transistor networks isNP-hard
Chakravarty, S.   He, X.   Ravi, S.S.  
Dept. of Comput. Sci., State Univ. of New York, Buffalo, NY;

This paper appears in: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publication Date: Jul 1991
Volume: 10,  Issue: 7
On page(s): 943-949
ISSN: 0278-0070
References Cited: 18
CODEN: ITCSDI
INSPEC Accession Number: 3988711
Digital Object Identifier: 10.1109/43.87604
Current Version Published: 2002-08-06

Abstract
Functional cells are a physical realization of complex MOS gates. Efficient algorithms for minimizing the width of a functional cell are known. Every solution to the width minimization problem leads to a cell of a certain height. It is shown that, even for functional cells of complex MOS gates represented by series-parallel transistor networks, the problem of finding a solution of minimum width that also minimizes the height is NP-hard

Index Terms
Available to subscribers and IEEE members.

References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
You are not logged in.
Guests may access Abstract records free of charge.
Login
Username
Password
» Forgot your password?
Please remember to log out when you have finished your session.
You must log in to access:
• Advanced or Author Search
• CrossRef Search
• AbstractPlus Records
• Full Text PDF
• Full Text HTML
Access this document
Full Text: PDF (620 KB)
» Buy this document now
»  Learn more about
»  Learn more about
    purchasing articles
    and standards

Rights and Permissions
» Learn More
Download this citation
Available to subscribers and IEEE members.
 
arrow_leftView TOC   |  Back to toparrow_up
Indexed by IEE Inspec
© Copyright 2009 IEEE – All Rights Reserved