Test set compaction algorithms for combinational circuits
Hamzaoglu, I.
Patel, J.H.
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL;
Abstract
This paper presents a new algorithm, essential fault reduction,
for generating compact test sets for combinational circuits under the
single stuck-at fault model, and a new heuristic for estimating the
minimum single stuck-at fault test set size. These algorithms together
with the dynamic compaction algorithm are incorporated into an advanced
automatic test pattern generation system for combinational circuits,
called MinTest. MinTest found better lower bounds and generated smaller
test sets than the previously published results for the ISCAS85 and full
scan versions of the ISCAS89 benchmark circuits
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