Architectural and compiler techniques for energy reduction inhigh-performance microprocessors
Bellas, N.
Hajj, I.N.
Polychronopoulos, C.D.
Stamoulis, G.
Digital/DNA Syst. Archit. Lab., Motorola Inc., Schaumburg, IL;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publication Date: Jun 2000
Volume: 8,
Issue: 3
On page(s): 317-326
Meeting Date: 08/16/1999 - 08/17/1999
Location: San Diego, CA, USA
ISSN: 1063-8210
References Cited: 20
CODEN: IEVSE9
INSPEC Accession Number: 6642820
Digital Object Identifier: 10.1109/92.845897
Current Version Published: 2002-08-06
Abstract
In this paper, we focus on low-power design techniques for
high-performance processors at the architectural and compiler levels. We
focus mainly on developing methods for reducing the energy dissipated in
the on-chip caches. Energy dissipated in caches represents a substantial
portion in the energy budget of today's processors. Extrapolating
current trends, this portion is likely to increase in the near future,
since the devices devoted to the caches occupy an increasingly larger
percentage of the total area of the chip. We propose a method that uses
an additional minicache located between the I-Cache and the central
processing unit (CPU) core and buffers instructions that are nested
within loops and are continuously otherwise fetched from the I-Cache.
This mechanism is combined with code modifications, through the
compiler, that greatly simplify the required hardware, eliminate
unnecessary instruction fetching, and consequently reduce signal
switching activity and the dissipated energy. We show that the
additional cache, dubbed L-Cache, is much smaller and simpler than the
I-Cache when the compiler assumes the role of allocating instructions to
it. Through simulation, we show that for the SPECfp95 benchmarks, the
I-Cache remains disabled most of the time, and the “cheaper”
extra cache is used instead. We also propose different techniques that
are better adapted to nonnumeric nonloop-intensive code
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