Retargetable estimation scheme for DSP architecture selection
Ghazal, N.
Newton, R.
Rabaey, J.
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;
This paper appears in: Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Publication Date: 2000
On page(s): 485-489
Meeting Date: 01/25/2000 - 01/28/2000
Location: Yokohama, Japan
ISBN: 1-58113-187-9
References Cited: 15
INSPEC Accession Number: 6597051
Digital Object Identifier: 10.1109/ASPDAC.2000.835148
Current Version Published: 2002-08-06
Abstract
Given the recent wave of innovation and diversification in digital
signal processor (DSP) architecture, the need for quickly evaluating the
true potential of considered architectural choices for a given
application has been rising. We propose a new scheme, called
retargetable estimation, that involves analysis of a high-level
description of a DSP application, with aggressive optimization search,
to provide a performance estimate of its optimal implementation on the
architectures considered. With this scheme, we present a new
parameterized architecture model that allows quick retargeting to a wide
range of architectural choices, and that emphasizes capturing an
architecture's salient optimizing features. We show that for a set of
DSP benchmarks and two full applications, hand-optimized performance can
be predicted reliably. We applied this scheme to two different
processors
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