High performance 0.18 /spl mu/m SOI CMOS technology

A 0.18 /spl mu/m SOI CMOS technology is presented. Key features in this technology are: more aggressive gate lithography (equivalent to 0.15 /spl mu/m half pitch generation) and devices than previously reported 0.18 /spl mu/m CMOS technology, low dose SIMOX SOI substrate, dual gate oxide, low /spl epsi/ BEOL insulator, and 7 layer copper metalization. Inverter delay of less than 6.5 ps has been achieved with this technology. A POWER4/sup TM/ test chip was built using the 0.18 /spl mu/m SOI technology and has demonstrated performance above 1 GHz.