Analog VLSI model of binaural hearing
Mead, C.A.
Arreguit, X.
Lazzaro, J.
California Inst. of Technol., Pasadena, CA;
This paper appears in: Neural Networks, IEEE Transactions on
Publication Date: Mar 1991
Volume: 2,
Issue: 2
On page(s): 230-236
ISSN: 1045-9227
References Cited: 11
CODEN: ITNNEP
INSPEC Accession Number: 3924017
Digital Object Identifier: 10.1109/72.80333
Current Version Published: 2002-08-06
Abstract
The stereausis model of biological auditory processing is proposed
as a representation that encodes both binaural and spectral information
in a unified framework. A working analog VLSI chip that implements this
model of early auditory processing in the brain is described. The chip
is a 100000-transistor integrated circuit that computes the stereausis
representation in real time, using continuous-time analog processing.
The chip receives two audio inputs, representing sound entering the two
ears, computes the stereausis representation, and generates output
signals that can directly drive a color CRT display. Outputs from the
chips for a variety of artificial and speech stimuli are shown
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