An alternative method for electro-thermal circuit simulation

In recent years great attention has been paid to the thermal issues in electronics design on system, board, package and chip level, including thermal and electro-thermal simulation of integrated circuits and MCM-s, or even integrated microsystems. In this paper we address some algorithmic issues regarding the method of simultaneous iteration. With the node reduction algorithm outlined here, electro-thermal simulation of large problems becomes feasible. Besides this algorithmic innovation, we provide a specification for a modular, platform independent electro-thermal simulator.