FPGA implementation of a variable step-size affine projection algorithm for acoustic echo cancellation

This paper presents a field-programmable gate array (FPGA) implementation of a recently proposed variable step-size affine projection algorithm (VSS-APA), in the context of acoustic echo cancellation. The proposed hardware implementation scheme takes advantage of the algorithm's specific features. Area and speed results are provided for the Xilinx Virtex 5 XC5VFX70T chip from the Xilinx ML507 evaluation board, when considering the particular case of the projection order p = 2. The overall performance of this acoustic echo canceller (AEC) indicates that it could be a reliable solution for real-world acoustic echo cancellation scenarios.