MIMO signal processing on a reconfigurable architecture

In this paper the implementation of multiple-input multiple-output (MIMO) signal processing on a reconfigurable hardware architecture is discussed. The implementation of MIMO systems is usually determined by the parameters of the application at hand, e.g. the number of sensor elements, the number of output signals or the required word length. Furthermore, there is also a flexibility in terms of the algorithms, which are used for computing the required task. We will present two different approaches for solving the linearly constrained MVDR (minimum variance distortionless response) beamforming problem. The two methods can be mapped on a reconfigurable hardware architecture. This architecture is described as a virtual systolic array, which consists of reconfigurable processor elements that can execute different transformation modes (linear, orthogonal). We will discuss the configuration in terms of change of parameters and change of algorithm, respectively. Furthermore, bit true simulations of the BER for the different approaches are presented for various word lengths. Finally, the trade-off between performance and reconfiguration effort is discussed.