Performance evaluation of battery balancing hardware

In this paper we evaluate the performance of seven proposed hardware topologies for balancing the cells in a battery pack. We consider four classes of battery balancing hardware; shunting, cell-to-stack, storage element, and dissipative hardware. We present models of these hardware topologies that capture the steady-state behavior of the balancing hardware dynamics. We evaluate the hardware topologies based on time required to balance the cells and energy dissipated during balancing. A linear programming based method for calculating the worst-case time to balance and energy dissipated during balance is provided. The number of linear programs required to compute both metrics grows exponentially with the number of cells. We show how to use symmetries to efficiently compute both metrics. Our approach scales well for large-scale battery packs and provides non intuitive solutions.