A 0.35μm CMOS 6-bit current steering DAC

This paper presents the design and experimental results of a high speed, low-power, thermometer coded and current steered 6-bit digital-to-analog converter (DAC). It is based on a hybrid architecture with a switched current matrix controlled by the four most significant digital bits, and a conventional 2-bit current source controlled by the two least significant bits. The DAC occupies 0.15 mm
²
chip area in standard 0.35 μm Complementary metal-oxide-semiconductor (CMOS) technology. A spurious-free dynamic range (SFDR) of 25 dB has been measured over the complete Nyquist interval at sampling frequencies up to 800 MS/s with a power consumption of 165 mW at 3.3 V power supply.