An analog dynamic memory array for neuromorphic hardware

We describe an array of capacitor based cells capable of storing analog voltages and currents for highly configurable large-scale neuromorphic hardware. A novel refresh scheme based on content-addressable memory as well as a slow and simple voltage ramp generator is presented. The circuits have been simulated in a 65nm mixed-signal low power process. Key characteristics are an area consumption of 175 μm
²
and a power consumption of less than 125nW per stored value. A prototype chip has been designed and submitted for fabrication.