A novel inter-layer intra prediction architecture for real-time SVC video codecs

Scalable Video Coding (SVC) is an extension of H.264/AVC standard proposed by Joint Video Team (JVT) to provide flexibility and adaptability on video transmission. For this purpose, this standard exploits the use of layers, what permits to obtain a bit-stream where enhancement layers can be considered to obtain an output video sequence with a higher resolution (temporal or spatial) and/or a higher quality/fidelity. Unfortunately, this versatility comes at the price of an increase in the computational cost of SVC-compliant encoders and decoders, seriously jeopardizing their utilization in applications under tight real-time constraints. To alleviate this problem, this paper proposes a novel inter-layer intra prediction hardware architecture devoted to perform the up-sampling operations in spatially scalable SVC codecs, as this type of scalability has demonstrated to be the most computationally complex of the three types of scalability included in the SVC standard. The proposed architecture has been implemented onto a low-cost FPGA device, being able to process a HDTV 1080p@30fps video sequence at a working frequency as low as 50 MHz. Moreover, as opposed to the static solutions found in the state-of-the-art, the hardware resources of our design can be easily adapted to the processing requirements demanded by the characteristics of the video sequence to be processed, avoiding the waste or the lack of resources in case these requirements become less or more demanding, respectively. These characteristics, together with the utilization of AMBA AXI standard interfaces, definitely convert our architecture into a proper IP module ready to be integrated in a SVC-based video compression system-on-a-chip (SoC).