Real-time FPGA implementation of efficient filter-banks for digitally sub-banded coherent DFT-S OFDM receiver

We demonstrate a real-time FPGA realization of dual polarization filter banks - this high-speed 2×25 GBd low-complexity core establishes feasibility of energy-efficient (multipliers count ~halved) HW architecture for a digitally sub-banded 170 Gb/s DFT-S OFDM receiver.