Many-core parallelization of fixed-point optimization of VLSI circuits through GPU devices

Fixed-point arithmetic is selected for the implementation of low-cost, high-performance VLSI circuits devoted to signal and image processing. In order to produce highly optimized systems, fixed-point optimization is applied. During the optimization loop, the mathematical error produced by finite word-lengths is continuously assessed, leading to long design times. Thus, it is essential to speedup error estimation. In this paper, the parallelization of fixed-point optimization using last-generation GPU devices is addressed. Speedups up to ×58 are achieved when compared to 1 Intel core. Two different CUDA implementations are tested. The capabilities of GPUs to perform fixed-point optimization are analyzed, providing limits to the maximum complexity of the fixed-point circuits that can be handled.