Decimation filter with novel MVTL XOR gate
Xie, Y.P.
Van Duzer, T.
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA;
This paper appears in: Applied Superconductivity, IEEE Transactions on
Publication Date: Jun 1997
Volume: 7,
Issue: 2, Part 3
On page(s): 2480-2483
Meeting Date: 08/25/1996 - 08/30/1996
Location: Pittsburgh, PA, USA
ISSN: 1051-8223
References Cited: 7
CODEN: ITASE9
INSPEC Accession Number: 5682787
Digital Object Identifier: 10.1109/77.621742
Current Version Published: 2002-08-06
Abstract
A single-rail Modified Variable Threshold Logic (MVTL) decimation
filter is designed by employing a novel XOR gate, which overcomes the
difficulty of the lack of a good inverter in the MVTL logic family. A
10-bit deep-pipelined decimation filter consisting of about 700
junctions in a 5 mm×5 mm chip with power consumption of 0.4 mW is
designed
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