Use of selective precharge for low-power content-addressable memories

A general technique to reduce the energy used by individual CMOS logic gates in large fan-in logic arrays is derived, and applied to the comparators in a content-addressable memory (CAM), an important application where power dissipation is often large and the technique works particularly well. A small subset of the inputs are removed from the large parallel pulldown switch and used to control the precharge instead, greatly reducing the number of cycles requiring a full charge/discharge sequence in many cases, with only a modest delay penalty. Estimates of the optimal number of bits to remove and the performance gain as a function of various parameters are provided.