Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection

The paper discusses a technique to perform efficient circuit reliability analysis of large analog and mixed-signal systems. The proposed method includes the impact of both process variations and transistor aging effects. The complexity of large systems is dealt with by partitioning the system into manageable subblocks that are modeled separately. These models are then evaluated to obtain the system specifications. However, highly expensive reliability simulations, combined with nonlinear output behavior and the high dimensionality of the problem is still a very challenging task. Therefore the use of fast function extraction symbolic regression (FFX) is proposed. This allows to capture the high-dimensional nonlinear problem with good accuracy. Also, an active learning sample selection algorithm is introduced to minimize the amount of expensive aging simulations. The algorithm trades of space exploration with function nonlinearity detection and model uncertainty reduction to select optimal model training samples. The simulation method is demonstrated on a 6 bit Flash ADC, designed in a 32nm CMOS technology. Experimental results show a speedup of 360× over existing aging simulators to evaluate 100 Monte-Carlo samples with good accuracy.

I. Introduction

For over three decades, scientists have been scaling CMOS devices to increasingly smaller feature sizes to meet requirements on speed, complexity, circuit density and power consumption demanded by many advanced applications. However, going to these ultra-scaled CMOS devices also comes at a cost. Guaranteeing circuit reliability over the entire lifetime of a system is one of the major challenges designers are faced with today [1], [2]. Circuit reliability issues can be categorized into spatial and temporal unreliability effects [2]. The former are related to process variability and are fixed in time and visible right after production. These effects depend on circuit layout, neighboring environment and process conditions, impact the geometry and structure of the circuit and can lead to yield loss. Temporal unreliability effects, on the other hand, are timevarying and change depending on operating conditions such as operating voltage, temperature, switching activity, presence and activity of neighboring circuits.