A compact calorimeter trigger for the ATLAS detector

A design of a compact first level calorimeter trigger for the ATLAS LHC-detector is presented. The highly parallel pipelined system is based on 4096 systolic processors partitioned into 256 weakly interacting processing ASICs. Data enters the system on 4096 fibers at 800 Mb/s. The fibers are split in two and routed to 16 processing boards where they enter opto-electric converter modules. Each such converter translates data from 8 fibers into 8 differential signals which are sent to a processing ASIC. These high speed signals are received by bipolar input circuits, while the main data processing is performed in CMOS at a lower speed (320 MHz). A 0.5 /spl mu/m BiCMOS process with 4 metal layers, available at the Ericsson Component foundry, is used for the implementation. A demonstrator program involving the production of several test ASICs has been initiated to prove the viability of the design. Although the ATLAS collaboration has recently (summer 1996) chosen an alternative, distributed processor design based on more proven techniques and requiring less R&D work, the compact trigger concept is still of interest for upgrades and future detectors, and development continues towards a point where its feasibility can be evaluated.