A solution methodology for exact design space exploration in athree-dimensional design space
Chaudhuri, S.
Blthye, S.A.
Walker, R.A.
Dept. of Electr. Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publication Date: Mar 1997
Volume: 5,
Issue: 1
On page(s): 69-81
Meeting Date: 09/13/1995 - 09/15/1995
Location: Cannes, France
ISSN: 1063-8210
References Cited: 41
CODEN: IEVSE9
INSPEC Accession Number: 5525489
Digital Object Identifier: 10.1109/92.555988
Current Version Published: 2002-08-06
Abstract
This paper describes an exact solution methodology, implemented in
Rensselaer's Voyager design space exploration system, for solving the
scheduling problem in a three-dimensional (3-D) design space: the usual
two-dimensional (2-D) design space (which trades off area and schedule
length), plus a third dimension representing clock length. Unlike design
space exploration methodologies which rely on bounds or estimates, this
methodology is guaranteed to find the globally optimal solution to a 3-D
scheduling problem. Furthermore, this methodology efficiently prunes the
search space, eliminating provably inferior design points through the
following: 1) a careful selection of candidate clock lengths and 2)
tight bounds on the number of functional units or on the schedule
length. Both chaining and multicycle operations are supported
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