CUDA-based AES parallelization with fine-tuned GPU memory utilization

Current Graphics Processing Unit (GPU) presents large potentials in speeding up computationally intensive data parallel applications over traditional parallelization approaches since there are much more hardware threads inside GPUs than the computational cores available to common CPU threads. NVIDIA developed a generic GPU programming platform, CUDA, which allows programmers to utilize GPU through C programming language and parallelize applications in a similar way as in traditional multithreading approach. However, not all applications are suitable for this new platform. Only computationally intensive applications without strong dependency are good candidates. Although Advanced Encryption Standard (AES) does not belong to this group due to the light workload in its efficient implementation, this paper proposed an approach to arrange data in different GPU memory spaces properly, overcoming the extra communication delay, and still turning GPU into an effective accelerator. Experimental results have demonstrated its effectiveness by performance gains and proved that GPU can be used to accelerate more types of applications.

I. Introduction

As computers and networks have reached each corner of human life geographically and practically, security and privacy become major concerns. Traditional data encryption/decryption is a computationally intensive task. Since it takes up lots of resources on the computing and communication endpoints, both computation and communication activities can be slowed down. Therefore, faster and more secure cryptographic algorithms are on demand. Advanced Encryption Standard (AES) is one of such widely used symmetric key cryptographic algorithms. It has reduced the computational operations dramatically in data encryption and decryption whereas its implementation structure exhibits a high degree of data parallelism for further performance elaboration. Theo-retically, AES is an extra burden for security and its execution time should be reduced. Further accelerator is expected to exploit its rich parallelism.