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Simultaneous multithreading: Maximizing on-chip parallelism
Tullsen, D.M.   Eggers, S.J.   Levy, H.M.  
Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA;

This paper appears in: Computer Architecture, 1995. Proceedings. 22nd Annual International Symposium on
Publication Date: 22-24 Jun 1995
On page(s): 392- 403
ISSN: 1063-6897
ISBN: 0-89791-698-0
INSPEC Accession Number: 5086803
Current Version Published: 2005-05-23

Abstract
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a single cycle. We present several models of simultaneous multithreading and compare them with alternative organizations: a wide superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing architectures. Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor. Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multi-threading. We evaluate several cache configurations made possible by this type of organization and evaluate tradeoffs between them. We also show that simultaneous multithreading is an attractive alternative to single-chip multiprocessors; simultaneous multithreaded processors with a variety of organizations outperform corresponding conventional multiprocessors with similar execution resources. While simultaneous multithreading has excellent potential to increase processor utilization, it can add substantial complexity to the design. We examine many of these complexities and evaluate alternative organizations in the design space.

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