A switched capacitor implementation of the generalized linear integrate-and-fire neuron
Folowosele, F.
Harrison, A.
Cassidy, A.
Andreou, A.G.
Etienne-Cummings, R.
Mihalas, S.
Niebur, E.
Hamilton, T.J.
Electr. & Comput. Eng. Dept., Johns Hopkins Univ., Baltimore, MD, USA;
This paper appears in: Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Publication Date: 24-27 May 2009
On page(s): 2149-2152
Location: Taipei,
ISBN: 978-1-4244-3827-3
INSPEC Accession Number: 10760951
Digital Object Identifier: 10.1109/ISCAS.2009.5118221
Current Version Published: 2009-06-26
Abstract
In this paper we present the circuits and simulation results for a silicon neuron which is based on a modified version of the Mihalas-Niebur neural model. This silicon neuron produces 15 of the 20 known neural spiking and bursting behaviors. It has low complexity and reliable matching and can thus be easily integrated into more complex neuromorphic systems. Implemented in a 0.15 mum 1.5 V CMOS process, each neuron consumes about 7.5 nW of power at 1 kHz and occupies an area of 70 mum by 70 mum.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
