Direct extraction of interface trap states from the low frequency gate C-V characteristics of MOS devices with ultrathin high-К gate dielectrics

A simple but accurate D
_it
extraction technique has been proposed from low frequency C-V characteristics of MOS devices with ultrathin high-K gate dielectrics. The proposed method incorporates quantum mechanical effect with wave function penetration for theoretical calculation of MOS electrostatics. Fermi-Dirac distribution function and the effect of finite temperature have also been included in the proposed technique. The extraction technique has been applied to different simulated devices with different Dit profiles. Excellent agreement has been found between extracted and actual D
_it
profiles.