TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
Czutro, A.
Polian, I.
Lewis, M.
Engelke, P.
Reddy, S.M.
Becker, B.
Inst. for Comput. Sci., Albert-Ludwigs-Univ., Freiburg;
This paper appears in: VLSI Design, 2009 22nd International Conference on
Publication Date: 5-9 Jan. 2009
On page(s): 227-232
Location: New Delhi,
ISSN: 1063-9667
ISBN: 978-0-7695-3506-7
INSPEC Accession Number: 10399930
Digital Object Identifier: 10.1109/VLSI.Design.2009.20
Current Version Published: 2009-01-19
Abstract
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models.
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