Simulation Study on the Effect of Multiple Node Charge Collection on Error Cross-Section in CMOS Sequential Logic
Casey, M.C.
Duncan, A.R.
Bhuva, B.L.
Robinson, W.H.
Massengill, L.W.
Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN;
This paper appears in: Nuclear Science, IEEE Transactions on
Publication Date: Dec. 2008
Volume: 55,
Issue: 6, Part 1
On page(s): 3136-3140
ISSN: 0018-9499
INSPEC Accession Number: 10467220
Digital Object Identifier: 10.1109/TNS.2008.2005895
Current Version Published: 2009-01-19
Abstract
A technique for estimating error cross-section for combinational circuits based on charge collection at multiple nodes is presented. Ordinarily, charge collection from an ion strike is assumed to occur only on a single node, but with decreasing feature sizes in nanometer technologies, charge sharing among devices is worsening, leading to charge collection on multiple nodes. When multiple SETs are considered, simulation results show a 380times increase in cross-section with a four-bit carry look-ahead generator, and a 27times increase with a four-bit arithmetic logic unit. Additionally, both circuits show a linear increase in cross-section as frequency increases.
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