Integrated circuit design with NEM relays
Chen, F.
Hei Kam
Markovic, D.
Tsu-Jae King Liu
Stojanovic, V.
Alon, E.
Dept. of EECS, Massachusetts Inst. of Technol., Cambridge, MA;
This paper appears in: Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
Publication Date: 10-13 Nov. 2008
On page(s): 750-757
Location: San Jose, CA,
ISSN: 1092-3152
ISBN: 978-1-4244-2819-9
INSPEC Accession Number: 10394990
Digital Object Identifier: 10.1109/ICCAD.2008.4681660
Current Version Published: 2008-11-18
Abstract
To overcome the energy-efficiency limitations imposed by finite sub-threshold slope in CMOS transistors, this paper explores the design of integrated circuits based on nano-electro-mechanical (NEM) relays. A dynamical Verilog-A model of the NEM relay is described and correlated to device measurements. Using this model we explore NEM relay design strategies for digital logic and I/O that can significantly improve the energy efficiency of the whole VLSI system. By exploiting the low effective threshold voltage and zero leakage achievable with these relays, we show that NEM relay-based adders can achieve an order of magnitude or more improvement in energy efficiency over CMOS adders with ns-range delays and with no area penalty. By applying parallelism, this improvement in energy-efficiency can be achieved at higher throughputs as well, at the cost of increased area. Similar improvements in high-speed I/O energy are also predicted by making use of the relays to implement highly energy-efficient digital-to-analog and analog-to-digital converters.
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