Diastolic arrays: Throughput-driven reconfigurable computing
Myong Hyon Cho
Chih-Chi Cheng
Kinsy, M.
Suh, G.E.
Devadas, S.
Massachusetts Inst. of Technol., Cambrige, MA;
This paper appears in: Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
Publication Date: 10-13 Nov. 2008
On page(s): 457-464
Location: San Jose, CA,
ISSN: 1092-3152
ISBN: 978-1-4244-2819-9
INSPEC Accession Number: 10394946
Digital Object Identifier: 10.1109/ICCAD.2008.4681615
Current Version Published: 2008-11-18
Abstract
Diastolic arrays are arrays of processing elements that communicate exclusively through First-In First-Out (FIFO) queues. FIFO virtualization units enable relaxed timing of data transfers, and include hardware support to guarantee bandwidth and buffer space for all data transfers, which may follow composite paths through the network. We show that the architecture of diastolic arrays enables efficient synthesis from high-level specifications of communicating finite state machines so average throughput is maximized. Preliminary results are presented on an H.264 decoding benchmark.
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