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Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
Walter, D. Little, S. Myers, C. Seegmiller, N. Yoneda, T.
Univ. of Northern Philippines, Vigan;

This paper appears in: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publication Date: Dec. 2008
Volume: 27, Issue: 12
On page(s): 2223-2235
Location: Sonoma, CA, USA,
ISSN: 0278-0070
INSPEC Accession Number: 10313279
Digital Object Identifier: 10.1109/TCAD.2008.2006159
Current Version Published: 2008-11-18

Abstract
This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits. The first model checker utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver. Both methods have been implemented, and preliminary results are promising.

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